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Does anyone has source code of asyn fifo?
by Unknown on Aug 11, 2007 |
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hi,
i have a problem of somewhat the same type. I have designed a
256*8 RAM and while implementing it on Spartan 2 , how to give 8 bit
data in and data out. ???? secondly to check i reduced the size to
256*4 and tried to give input at dipswitched anr while reading i am
trying to use seven segment LED but this thing not working with me.
tell????
----- Original Message -----
From: ramireddy8 at h...
To: ethmac at o...
Date: Thu, 23 Jan 2003 10:13:28 -0100
Subject: RE: [ethmac] Does anyone has source code of asyn fifo?
does any have the source code for asynchronous fifo??if so can some
one send me??
----- Original Message -----
From: "Illan Glasner" iglasner at z... >
To: ethmac at o... >
Date: Fri, 17 May 2002 12:15:59 -0700
Subject: RE: [ethmac] Does anyone has source code of asyn fifo?
>
> > > Hi, > > I can't say much about Vhdl simply since I use verilog, however as
> for 16x8 use 128 CLB well ... , why not simple instantiate a
> RAM16X8D this will take you for Spartan as well as Virtex/VirtexE
> only 8 CLB.
> > than of course on this you add your controler which you should be
> able to do just as good as xilinx do as well as you can get
exactly
> what you want and not what you have to get, meaning knowing
how and
> what you can sometime have in certain condition (like one
clock is
> always faster etc etc) even small design/usage.
> > or maybe for certain fifo an SLR16 will be a good solution whcih
> each SLR16 take one CLB so once again for 16x8 you will need 8
CLB
>
> of course you might want to even put it in one of the memorey and
> than the memorey itself cost you 0 CLB and only the controler
will
> require some.
> > as for fifo for not syntesisbale code than this is completly > different story as there is no need for synconization/gray/etc etc
> usage simple write soemthing like
> > always @ (posedge wclk) > if (we) > mem[wadd] > > always @ (posedge rclk) > do > // or maybe > // do > > Again maybe in VHDL this is comletly different story but I see no
> reason why not to design an synhesis your fifo ram rom etc
etc.
>
> have a nice day
>
> Illan
>
>
> -----Original Message-----
> From: Javier_castillo_villar at y...
> [mailto:Javier_castillo_villar at y... ]
> Sent: Friday, May 17, 2002 7:09 AM
> To: ethmac at o...
> Subject: RE: [ethmac] Does anyone has source code of asyn
fifo?
>
> > Hi: > It´s much better to use a coregen or megawizard fifo for your
> design.
> If you describe a fifo in vhdl and then you sinthetize it, you use
> a CLB
> for each bit you want to store, so if you are using a 16x8 fifo you
> are
> using at least ¡128 CLB!. If you use a core generator program you
> are
> using internal resources of the FPGA and special configurations of
> the
> CLBs. In this case you can easily store 16 bits or more in each
> CLB.
> You MUST NOT implement a memory in VHDL with a array, you have to
> generate a memory with coregen or megawizard or a program like
> this. > Your FPGA suplier offer it for free. > I am agree with you when you say an eng must know how to make a
> fifo but it´s not a good idea to sinthetize it.
>
> Nice day
>
>
>
>
>
>
> ----- Original Message -----
> From: "Illan Glasner" iglasner at z... >
> To: ethmac at o... >
> Date: Thu, 16 May 2002 19:32:05 -0700
> Subject: RE: [ethmac] Does anyone has source code of asyn
fifo?
>
>
> > > Hi, > > Two small comment : > > 1. > > Notice that using Coregen or Megawizard the memorey usage of
> your
> Unix machine (and I assume the same with PC but can't say
for
> sure
> as I use only Unix) is much more than simple use the
"pure"
> memorey
> and write your own fifo/mem-ctrl etc etc.
> > as for the timing it is just as good. > > 2. > BUT even more important why not try and do it yourself ? > > after all you chose to be an Eng so give it a try fight with
> this
> until you get it.
> > otherwise you become just as any other who know how to do what
> the
> Megawizard/Coregen can do, maybe also use IP core ...
> > Yes if you want to make 8/10 for sure use it as otherwise > writing
> the table by your own you will no doubt make dozen's of
typo
> but
> fifo are something very elementry and assuming you are
"new"
> to
> this most likely when you will try to get a new job (or
first
> job)
> you will be asked about such thing and I belive an answer
like
> "I
> press the megawizard or the coregen" will not be too
> impressing.
>
> have a nice day
>
> Illan
>
>
> -----Original Message-----
> From: Javier_Castillo_Villar at y...
>
>
[/cgi-bin/post.cgi?cmd=new&to=Javier_Castillo_Villar%20at%
> 20yahoo%20dot%20es&msg=/ml-archive/ethmac/msg00030.shtml]
> Sent: Thursday, May 16, 2002 9:54 AM
> To: ethmac at o...
> Subject: Re: [ethmac] Does anyone has source code of asyn
> fifo?
>
> > If you are using a xilinx fpga use coregen program to > generate
> it, if
> you are using a altera fpga use megawizard program. Both are
> free
> and
> they are suplied with the other xilinx or altera tools
>
> ----- Original Message -----
> From: zou.yixin at z...
> To: ethmac at o...
> Date: Mon, 13 May 2002 09:48:29 +0800
> Subject: [ethmac] Does anyone has source code of asyn
fifo?
>
> >
> > > > > > Hi, > > Does anyone has the source code of asynchronous fifo or
> somewhere
> > to find
> > it? > > Thanks. > > yxzhou > > > > |
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